Word line read disturb error reduction through fine grained access counter mechanism

ABSTRACT

An apparatus is described. The apparatus includes a solid state drive having multiple three dimensional stacked FLASH memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the FLASH memory chips at a granularity of segments of blocks of said FLASH memory chips that are coupled to a same word line and source gate source node to diminish word line read disturb errors.

RELATED CASES

This application is a divisional of and claims the benefit of U.S.patent application Ser. No. 15/627,928, entitled, “WORD LINE READDISTURB ERROR REDUCTION THROUGH FINE GRAINED ACCESS COUNTER MECHANISM”,filed Jun. 20, 2017, now U.S. Pat. No. 10,236,069, Issued Mar. 19, 2019which are incorporated by reference in their entirety.

FIELD OF INVENTION

The field of invention pertains generally to the computing sciences and,more specifically, to word line read disturb error reduction throughfine grained access counter mechanism.

BACKGROUND

As the storage densities of mass storage devices continues to increase,both data corruption error mechanisms and the manner of trying to avoidthem are becoming increasingly complex. An increasingly problematic datacorruption mechanism for high density FLASH memory devices is the wordline read disturb error mechanism. In the case of the word line readdisturb error mechanism, data kept by storage cells that are proximateto a cell being frequently accessed for read operations may becomecorrupted on account of the signaling being frequently applied to thecell.

FIGURES

A better understanding of the present invention can be obtained from thefollowing detailed description in conjunction with the followingdrawings, in which:

FIG. 1 shows circuit for a stacked storage cell;

FIG. 2a shows a cross section of a block of storage cells;

FIGS. 2b and 2c show pages stored by a storage cells;

FIG. 2d shows a solid state drive (SSD);

FIG. 3 shows an improved SSD;

FIG. 4 shows a first set of counter values for the improved SSD of FIG.3;

FIG. 5 shows a second set of counter values for the improved SSD of FIG.3;

FIG. 6 shows a third set of counter values for the improved SSD of FIG.3;

FIG. 7 shows a method performed by the SSD of FIG. 3;

FIG. 8 shows a computing system.

DETAILED DESCRIPTION

FIG. 1 shows a prior art circuit schematic for the storage cell regionof a three dimensional NAND FLASH memory. As observed in FIG. 1, thecircuit includes a stack of NAND FLASH storage cells 101 coupled betweena select gate source transistor 102 and a select gate drain transistor103. The select gate source transistor 102 is coupled to a source line104. The stack of storage cells 101 may be implemented as athree-dimensional stack of FLASH transistors that are monolithicallyintegrated as a three dimensional storage array on a semiconductor chipalong with the select gate source and select gate drain transistors 102,103 as well as other transistor devices (not shown) that help implementthe NAND function of the storage cell (e.g., sense amplifiers, rowdecoders, address decoders, etc.).

FIG. 2a shows an exemplary embodiment 200 of the physical layout of ablock of a three dimensional NAND FLASH storage cell array. Here, acomplete NAND FLASH memory may comprise a plurality of such blocks(e.g., thousands of such blocks). For example, a different block may beaccessed for each respective bit of a word of data that is written intoor read from the memory. Alternatively or in combination, different(e.g., higher order) address bits that are provided to the memory may bedecoded to activate different subsets of blocks within the overallmemory.

As observed in FIG. 2a , the storage cell array block 200 includes aplurality of storage columns 201 that each contain a stack of storagecells (also referred to as a column or pillar) where each storage cellin a same stack corresponds to a different “level” of the stack (fordrawing ease only the leftmost and rightmost stacks are labeled withreference number 201). Additionally, different levels of a stack arecoupled to different respective word lines and the same stack levelacross multiple stacks is coupled to a same word line. In the particularembodiment of FIG. 2a , each storage column contains four storagecells/levels in its respective stack. As such, four different word lines202_1 through 202_4 that each mark a different respective level of thestacks is coupled across the columns.

The physical layout of FIG. 2a shows that certain nodes of the genericstorage cell design of FIG. 1 are shared within a block. For example, inthe layout of FIG. 2a , all storage cell stacks in the block share thesame word lines 202_1 through 202_4, source node 203 and bit-line 204.

Additionally, the block of FIG. 2a can be viewed as being composed offour different sub-blocks 205_1 through 205_4 where the columns of eachrespective sub-block share the same select gate source node. That is, inthe embodiment of FIG. 2a , the columns of sub-block 205_1 share sameselect gate source node 206_1, the columns of sub-block 205_2 share sameselect gate source node 206_2, the columns of sub-block 205_3 share sameselect gate source node 206_3 and the columns of sub-block 205_4 sharesame select gate source node 206_4. In an embodiment, each stackincludes its own respective select gate source transistor but the gatenodes of these transistors within a same sub-block are tied to the sameselect gate source node.

Other nodes of a storage cell stack, however, are not shared amongst themultiple storage cell stacks of the block. Besides the storage cells ofthe stacks themselves, note that each storage cell stack in theparticular layout embodiment 200 of FIG. 2a has its own dedicated selectgate drain node 207. That is, in an embodiment, each storage cell stacknot only includes its own select gate drain transistor, but also, therespective gate node of each such select gate drain transistor isindividually controlled/driven and is not tied to the gate node of anyother select gate drain transistor within a same sub-block at least.

In order to access any particular storage cell within the block, such asa cell in the leftmost column in FIG. 2a as an example, the select gatesource node 206_1 of the targeted cell's sub-block is activated (SGS_SELin FIG. 2a ) and the select gate source node of the other threesub-blocks in the block are deactivated (SGD_DESEL in FIG. 2a ).Likewise, the respective select gate drain node of each storage columnin the three unselected sub-blocks is deactivated (SGD_SUBBLK in FIG. 2a). Additionally, the select gate drain node of the targeted cell'sstorage column is activated (SGD_SEL in FIG. 2a ) while all other selectgate drain nodes in the block are deactivated (SGD_DESEL in FIG. 2a ).Finally, the word line that is coupled to the targeted storage cell isactivated while the other word lines are de-activated.

Note that the horizontal X axis of FIG. 2a runs parallel to bit line204. A three dimensional NAND memory device extends the concept of ablock beyond the two-dimensional perspective of FIG. 2a into athree-dimensional structure having a width that extends along the Y axisin a direction that is orthogonal to the bit lines. The logical conceptof a “page” helps to define this additional block dimension.

FIGS. 2b and 2c depict the concept of a logical page. Here, multiplestorage cell columns 201 are observed in FIG. 2b along the Y axis. Thecross sectional “slice” of a full block depicted in FIG. 2a isrepresented as slice 200 in FIG. 2b . For ease of drawing the SGDtransistors are not shown in FIG. 2b but the block's bit lines BL0, BL1,etc. are depicted incrementing along the Y axis. As can be seen from thebit lines BL0 through BL(K−1), the block has a width along the Y axis ofK columns.

According to the perspective of FIG. 2b , a “page” of data is formedfrom the storage cells that reside at a same stack level and extendalong the Y axis (orthogonal to the bit lines). Thus, the data stored inthe group 210 of storage cells observed in FIG. 2b corresponds to one ormore pages of data. In the case where the FLASH devices each store onebit of information there is only one page of data per stack level. Thus,for instance, if the storage cells of group 210 each only store one bitof data there is only one page of data stored by the cells of group 210.

The storage cells of more recent FLASH memory technologies, however, aredesigned to store more than one bit. For example, in the case of triplelevel cell (TLC) FLASH technology, each FLASH storage cell stores threebits of data. Referring to FIG. 2c , if the FLASH devices of FIG. 2b areimplemented as TLC cells, there are three pages of data stored perlevel. Here, as observed in FIG. 2c , each FLASH device can be viewed asstoring an upper bit B1, a middle bit B2 and a lower bit B3 (in realityeach of the FLASH devices store one of eight different voltage levelseach of which correspond to a specific B1, B2, B3 bit pattern). As such,the same, group of storage cells 210 of FIG. 2b would keep 3 pages ofinformation: 1) a first page composed of the B1 bits, 2) a second pagecomposed of the B2 bits; and, 3) a third page composed of the B3 bits.

FIG. 2d shows an embodiment of a solid state drive (SSD) 220 thatincludes multiple, discrete stacked storage cell NAND FLASH memory chips222_1 through 222_N. The SSD 220 also includes a control function 221that implements the functions and operations performed by the SSD 200.Here, the control function 221 may be implemented with controllercircuitry that is implemented as a controller or processor that executesfirmware program code, dedicated hardware logic circuitry (e.g.,hardwired logic circuitry (e.g., application specific integrated circuit(ASIC)) and/or programmable logic circuitry (e.g., Field ProgrammableGate Array (FPGA), programmable logic device (PLD), programmable logicarray (PLA))), or, that executes control functions with a combination ofprogram code execution and hardware logic circuitry. Any program codethat is executed by the control function 221 may be locally stored innon volatile storage resources of the SSD. The SSD also includes a hostinterface 223 such as a PCIe link or other form of interconnect (e.g.,for connection to a host platform).

One of the responsibilities of the control function 221 is theimplementation of wear-leveling. As is known in the art, FLASH devicescan “wear out” (their ability to keep data becomes unreliable) if theyare accessed too frequently. As such, the control function 221implements a special algorithm that monitors how often each of thestorage cell blocks within each FLASH chip 222 are being accessed, and,“swaps” the data content of a more frequently accessed block with thedata content of a less frequently used block. By so doing, thereliability of the storage cells of the block that was storing the morefrequently accessed data is preserved because, after the swap, they willbe storing less frequently accessed data.

Traditionally, the control function 221 has maintained a counter foreach block within each FLASH chip 222 that increments each time itscorresponding block is accessed. Those blocks whose access countssurpass a first threshold are marked as candidate blocks whose datashould be swapped out for wear leveling purposes. Those blocks whoseaccess counts remain beneath a second threshold are marked as candidateblocks for receiving data from blocks whose counts surpass the firstthreshold. During an actual wear leveling swap, a blocks whose count isbelow the second threshold has its less frequently accessed data movedinto a block whose access count has surpassed the first threshold.

Another data reliability problem, referred to as “word line readdisturb”, results from a word line being accessed too frequently forread operations. When a word line is activated for a read operation oneor more storage cells that are directly tied to the word line areaccessed. Unfortunately, the access induces, e.g., high energy fieldsand/or voltage potentials, in and/or around certain storage cells thatare proximate to the accessed storage cell(s). In cases where aparticular word line is activated for read operations too frequently,such proximate storage cells can have their stored data corrupted (oneor more bits of the proximate storage cells can be flipped).

Unfortunately, preventing word line read disturb errors by way of theaforementioned block based access count mechanism described just aboveis becoming increasingly unfeasible. Specifically, traditionally, wordline read disturb error rates correlated fairly tightly with uniformblock errors induced from other kinds of block accesses. As aconsequence, block access count based wear leveling was sufficient toalso predict/avoid word line read disturb errors. With the smallerstacked storage cells of newer FLASH technologies, however, word lineread disturb error rates are becoming multiple factors higher thanuniform block errors rates (e.g., 16 times higher, 128 times higher,etc.). As such, a finer grained access counting mechanism that includes,e.g., some kind of word line access counting mechanism is warranted.

Because pages of information are recognized/understood by the controlfunction 221, one approach for counting word line accesses is to keep acounter for each page that is stored in each of the FLASH chips 222. Inthis case, whenever a specific page is accessed for a read operation,its specific counter is incremented. Unfortunately, this approach is notfeasible because the number of different counters that would need to bemaintained by the control function 221 is very large which, in turn,would devote too much of the control function's memory resources to thedifferent counter values.

For example, referring briefly back to FIG. 2a , at least one pagecounter would be kept for every observed crossing point between a wordline and a column. As there are 32 observed columns and 4 observed wordlines in FIG. 2a , at least 128 unique counters would need to bemaintained for the block of FIG. 2a . The block design of FIG. 2a isonly exemplary in that current, actual FLASH memory block designstypically include thousands of unique word line and column crossings. Asthere are typically thousands of blocks per FLASH chip, perhaps multiplemillions of unique counters would need to be maintained for an SSD.

Thus, in order to reduce the sheer number of counters, another approachis to use two counters: 1) a first counter of the form [die_ID;block_ID]; and, 2) a second counter of the form [block_ID; SGS-WL_ID].Here, for the first counter, die_ID is used to identify a particular oneof the FLASH chips 222_1 through 222_N in the SSD and block_ID is usedto identify a particular block within the chip identified by the die_ID.By contrast, for the second counter, block_ID corresponds to aparticular block within all of the SSD's FLASH chips 222 (also referredto as a “macroblock”) and SGS-WL_ID identifies a particular segment of aword line within the set of blocks identified by the block_ID whoserespective storage cell stacks are tied to a same SGS node (alsoreferred to an “SGS-WL segment”).

As there are thousands of blocks per FLASH device, the number ofcounters of the first type (hereinafter referred to as “per blockcounters”) should only be in the range of tens of thousands or less forSSD's having tens of FLASH chips or less. Furthermore, as there aretypically no more than hundreds of different SGS-WL segments within ablock and no more than thousands of blocks per FLASH chip, the number ofcounters of the second form (hereinafter referred to as “SGS-WL segmentcounters”) should be in the range of hundreds of thousands or less.Thus, the number of counters is dramatically reduced as compared to anapproach that tracks access counters for each page in the SSD.

FIG. 3 therefore shows an improved SSD 320 that includes a controlfunction 321, FLASH chips 322 and interface 323 as described above withrespect to FIG. 2d . The control function 321 of the SSD 320 of FIG. 3,however, has been further enhanced to maintain per block counters 324and SGS-WL segment counters 325 as described just above. The enhancedcontrol function 321 also implements new wear leveling processes in viewof the state of these counters 324, 325 as described immediately below.The control function 321 include controller circuitry

The per block counters 324 provide a read access count for each block inthe SSD and are akin to the counters used by traditional SSDs in thatthere are separate counters for each block within each die in the SSD.The SGS-WL counters 325 provide a respective read access count fordifferent SGS-WL segments across all the dies in the SSD and areparticularly insightful into the prediction of word line read disturberrors.

Referring briefly back to FIG. 2a , read line disturb errors have beenobserved to be particularly dependent on SGS node coupling. That is, ifa read access to a particular storage cell is going to cause a disturberror within another storage cell, there is a higher likelihood that theaccessed storage cell and the disturbed storage cell are coupled to asame SGS node (e.g., if the accessed storage cell and the disturbedstorage cell are located on the same column they share the same SGStransistor, or, if the storage cell and the disturbed storage cell arelocated on different columns, there is a higher probability that thegate nodes of their respective SGS transistors are tied to the same SGSnode).

For the particular block embodiment of FIG. 2a , each observed sub group205_1, 205_2, 205_3, 205_4 is defined by the columns that are tied to asame SGS node. That is, the columns of sub group 205_1 are tied to SGSnode 206_1, the columns of sub group 205_2 are tied to SGS node 206_2,the columns of sub group 205_3 are tied to SGS node 206_3, and thecolumns of sub group 205_4 are tied to SGS node 206_4.

The SGS-WL_ID notation of the SGS-WL counters indicates that there is aseparate counter reserved for each unique combination of word line andgroup of columns, across all the FLASH chips in the SSD, that are tiedto a same SGS node. As such there are 16 different counters maintainedfor the block structure of FIG. 2a . That is, there is one WL3 counterfor each of sub-groups 205_1, 205_2, 205_3 and 205_4 (four counters forWL3 total), there is one WL2 counter for each of sub-groups 205_1,205_2, 205_3 and 205_4 (four counters for WL2 total), there is one WL1counter for each of sub-groups 205_1, 205_2, 205_3 and 205_4 (fourcounters for WL1 total) and there is one WL0 counter for each ofsub-groups 205_1, 205_2, 205_3 and 205_4 (four counters for WL0 total).As there are 16 counters per block for this exemplary block, the totalnumber of SGS-WL counters would be 16×M where M is the number of blocksper FLASH chip (a unique SGS-WL counter is kept for each SGS-WL segmentacross all blocks in a FLASH chip).

Active avoidance of read disturb errors within the SSD can be achievedby observing the state of the per block and SGS-WL counters 324, 325 andimplementing specific wear level routines in response. Examples aredescribed immediately below. Here, the control function 321 alsoincludes threshold settings 326, are parameters that, e.g, are stored inthe SSD's non volatile storage and/or, e.g., BIOS firmware non volatilestorage of the SSD's host platform and loaded into the control functionduring bring up and/r power-on-reset of the SSD. The control function321 determines when triggering a wear leveling data swap is appropriateby repeatedly comparing the current state of counters 324 and 325 to thethreshold settings 326 (or calculations made from them).

1. Per Block Threshold and Block Wear Leveling.

The per block threshold is a first threshold setting and is repeatedlycompared against each of the per block counter values 324. If the valueof any one of the per block counters 325 surpasses the per blockthreshold, that data contained by that counter's corresponding block isswapped with the data of another block within the SSD 320 whosecorresponding per block counter is, e.g., especially low (e.g., beneathsome second threshold).

2. Per SGS-WL Threshold and SGS-WL Segment Wear Leveling.

The per SGS-WL threshold can be used to detect when a particular SGS-WLsegment of a block has received a sufficient number of read accesses tojustify the swapping of the segment's pages with the pages of anotherSGS-WL segment that has received a relatively low number of readaccesses.

In an embodiment, because SGS-WL counter values for a particular SGS-WLare accumulated across multiple chips of an SSD, an e.g., empiricallydetermined count threshold for the SGS-WL segment of a single chip isscaled upward depending on how evenly or unevenly read accesses to aparticular SGS-WL segment is distributed across the dies of the SSD. Assuch, in various embodiments, the control function 321 is provided thesingle die SGS-WL threshold as one of thresholds 326. The wear levelingalgorithms executed by the control function 321 then dynamicallyadjust/determine the thresholds that trigger wear leveling swaps forindividual SGS-WL segments based on the count state of the SGS-WLcounters 326 and the per block counters 325. Here, the per blockcounters 325 add insight into usage patterns within the SSD 320 that canbe used to refine the thresholds for specific SGS-WL segments. FIGS. 4through 7 demonstrate some examples.

Consider an example where the empirically determined single die SGS-WLthreshold corresponds to 3,000 read accesses for word line read disturberrors. Consider further an SSD having four FLASH chips in the SSD (N=4in FIG. 3). If the SGS-WL counter values and the per block countervalues together indicate that the read accesses to a particular SGS-WLsegment are being evenly distributed across all the dies of the SSD,then, the SSD can set a wear leveling threshold for the SGS-WL segmentthat is equal to the empirically determined single die SGS-WL thresholdmultiplied by the number of die within the SSD. Thus, for SGS-WLsegments that meet this environmental condition, wear leveling can betriggered if their corresponding SGS-WL counter value reaches a value of12,000 (3,000×4=12,000).

FIG. 4 shows an exemplary state for per the block counter values 401 ofa particular block within each of the four die having block_ID=300. Ascan be seen, read accesses to the block having block_ID=300 are evenlydistributed across the four FLASH chips in the SSD. FIG. 4 also showsexemplary SGS-WL counter states 402 that are tabulated concurrently withthe counter per block counter values 401. Here, the first column 411identifies a particular block across all of the FLASH chips and thesecond column 412 identifies the different SGS-WL segments within eachcorresponding block.

In the depicted SGS-WL counter values 402, the second column 412 isaligned with the exemplary block design of FIG. 2a . As such, there are16 different entries (00 through 15) for each entry of the first column411. Again, actual current FLASH memory chips may have hundreds ofsecond column entries per first column entry. The observed access countsin the third column 413 are the total across all FLASH chips within theSSD. As can be observed from the exemplary SGS-WL counter data 402,SGS-WL segment 00 has received a total of 12,000 reads across all of thechips in the SSD whereas all other SGS-WL segments have received onlyone read access apiece.

From the SGS-WL counters 402 it is clear that SGS-WL segment 00 isreceiving the vast majority of read accesses that are made to blockshaving ID=300 across all four chips. This means the total per blockcounts for block 300 observed in the read block counters 401 areapproximately tallies of the SGS-WL segment 00 by itself. Viewing thecounts 401, 402 in this manner it is clear that the accesses to SGS-WLsegment 00 are being evenly distributed across the dies. As such, theSGS-WL counter threshold for SGS-WL segment 00 sufficient to triggerpage data swapping of SGS-WL segment 00 within each of the four dieshould be set at the single chip threshold times the number of chips inthe SSD (e.g., 3,000×4=12,000).

If the per block counter state 501 of FIG. 5 existed instead of thefirst counter state 401 of FIG. 4 and if the SGS-WL counter state 502 ofFIG. 5 existed instead of the SGS-WL counter state 402 of FIG. 4, thedecision to swap the pages of SGS-WL segment 00 should be made at a muchlower threshold than 12,000 and should only affect SGS-WL segment 00within one of the dies rather than in all four of the dies.

Referring to the per block counter state 501, it is clear that die 0 isreceiving the vast majority of accesses to block 300. In this case, thedecision to swap the pages of SGS-WL segment 00 could be made at aSGS-WL counter value that is equal to the single die threshold (3,000)especially since all other SGS-WL segments within block 300 continue toshow little/no access. That is, combining the information from bothcounter value tables 501 and 502, it is clear that SGS-WL segment 00 ofblock 300 of die 0 has received all 3,000 accesses to block 300 of die0. Therefore, the threshold for the SGS-WL counter value that triggersthe swapping of the pages of SGS-WL segment 00 should be set at 3,000instead of 12,000 and should only affect SGS-WL segment 00 within die 0.Thus, whereas the scenario of FIG. 4 triggers the page swapping formultiple physical SGS-WL segments, by contrast, the scenario of FIG. 5causes the swapping of the pages for only one physical SGS-WL segments.

Other scenarios that result in SGS-WL counter thresholds that residesomewhere between the extremes of FIGS. 4 and 5 can also be handled.FIG. 6 shows SGS-WL counter states 602 for another scenario where SGS-WLsegment 00 continues to receive substantially all the accesses to block300 across all the dies in the SSD. However, from the per block counterstates 601, these accesses are split across two of the die within theSSD. In this case, the appropriate second counter threshold for SGS-WLsegment 00 is twice the single die threshold (2×3,000=6,000) since it isclear that only until the SGS-WL counter for segment 00 reaches a valueof 6,000 will any particular one of the segments on any particular oneof the two die receive 3,000 accesses. If/when the SGS-WL counter forsegment 00 reaches 6,000, the pages of SGS-SL segment 00 should only beswapped for die 0 and 1 and not for die 2 and 3.

With respect to the aforementioned page swapping, when the storage cellsalong a particular SGS-WL are swapped out, all of the pages contained byeach of the cells is swapped out. Thus, for instance, in the case of TLCFLASH technology, three pages are swapped out per cell.

FIG. 7 shows a method described above. The method includes maintaining701 access counts to segments of blocks of FLASH memory chips of a solidstate drive that are coupled to a same word line and source gate sourcenode. The method includes determining 702 that a wear leveling thresholdhas been crossed for one of the segments. The method also includescausing 703 data stored in the one of said segments to be swapped out ofthe one of the segments to diminish word line read disturb errorsattributable to the one of said segments.

FIG. 8 shows a depiction of an exemplary computing system 800 such as apersonal computing system (e.g., desktop or laptop) or a mobile orhandheld computing system such as a tablet device or smartphone, or, alarger computing system such as a server computing system.

As observed in FIG. 8, the basic computing system may include a centralprocessing unit 801 (which may include, e.g., a plurality of generalpurpose processing cores and a main memory controller disposed on anapplications processor or multi-core processor), system memory 802, adisplay 803 (e.g., touchscreen, flat-panel), a local wiredpoint-to-point link (e.g., USB) interface 804, various network I/Ofunctions 805 (such as an Ethernet interface and/or cellular modemsubsystem), a wireless local area network (e.g., WiFi) interface 806, awireless point-to-point link (e.g., Bluetooth) interface 807 and aGlobal Positioning System interface 808, various sensors 809_1 through809_N (e.g., one or more of a gyroscope, an accelerometer, amagnetometer, a temperature sensor, a pressure sensor, a humiditysensor, etc.), a camera 810, a battery 811, a power management controlunit 812, a speaker and microphone 813 and an audio coder/decoder 814.

An applications processor or multi-core processor 850 may include one ormore general purpose processing cores 815 within its CPU 801, one ormore graphical processing units 816, a memory management function 817(e.g., a memory controller) and an I/O control function 818. The generalpurpose processing cores 815 typically execute the operating system andapplication software of the computing system. The graphics processingunits 816 typically execute graphics intensive functions to, e.g.,generate graphics information that is presented on the display 803. Thememory control function 817, which may be referred to as a main memorycontroller or system memory controller, interfaces with the systemmemory 802. The system memory 802 may be a multi-level system memory.

Each of the touchscreen display 803, the communication interfaces804-807, the GPS interface 808, the sensors 809, the camera 810, and thespeaker/microphone codec 813, 814 all can be viewed as various forms ofI/O (input and/or output) relative to the overall computing systemincluding, where appropriate, an integrated peripheral device as well(e.g., the camera 810). Depending on implementation, various ones ofthese I/O components may be integrated on the applicationsprocessor/multi-core processor 850 or may be located off the die oroutside the package of the applications processor/multi-core processor850. Non volatile storage 820 may include non volatile mass storagewhich may include one or more three dimensional FLASH SSDs having dualcounters to implement fine grained wear leveling as described at lengthabove. Non volatile storage 820 may hold the BIOS and/or firmware of thecomputing system.

One or more various signal wires within the computing system, e.g., adata or address wire of a memory bus that couples the main memorycontroller to the system memory, may include a receiver that isimplemented as decision feedback equalizer circuit that internallycompensates for changes in electron mobility as described above.

Embodiments of the invention may include various processes as set forthabove. The processes may be embodied in machine-executable instructions.The instructions can be used to cause a general-purpose orspecial-purpose processor to perform certain processes. Alternatively,these processes may be performed by specific hardware components thatcontain hardwired logic for performing the processes, or by anycombination of programmed computer components and custom hardwarecomponents.

Elements of the present invention may also be provided as amachine-readable medium for storing the machine-executable instructions.The machine-readable medium may include, but is not limited to, floppydiskettes, optical disks, CD-ROMs, and magneto-optical disks, FLASHmemory, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards,propagation media or other type of media/machine-readable mediumsuitable for storing electronic instructions. For example, the presentinvention may be downloaded as a computer program which may betransferred from a remote computer (e.g., a server) to a requestingcomputer (e.g., a client) by way of data signals embodied in a carrierwave or other propagation medium via a communication link (e.g., a modemor network connection).

1. A machine readable storage medium containing program code that whenexecuted by a controller of a solid state drive causes a method to beperformed, said method comprising: maintaining access counts to segmentsof blocks of FLASH memory chips of said solid state drive that arecoupled to a same word line and source gate source node; determiningthat a wear leveling threshold has been crossed for one of saidsegments; and, causing data stored in said one of said segments to beswapped out of said one of said segments to diminish word line readdisturb errors attributable to said one of said segments.
 2. The machinereadable storage medium of claim 1 wherein the method further comprisesadaptively adjusting said wear leveling threshold based on a count valueof said access counts.
 3. The machine readable storage medium of claim 2wherein the method further comprises maintaining different access countsfor different blocks within different ones of said FLASH memory chips.4. The machine readable storage medium of claim 3 wherein the methodfurther comprises adaptively adjusting said wear leveling thresholdbased on a count value of said access counts and said different accesscounts.
 5. The machine readable medium of claim 2 wherein the methodfurther comprises adjusting how many of said segments are to have theirrespective data swapped out in response to said wear leveling thresholdhaving been crossed.
 6. The machine readable medium of claim 2 whereinsaid adaptively adjusting further comprises adjusting the threshold inresponse to accesses to same positioned ones of said segments withinsame blocks across multiple ones of said FLASH memory chips being evenlydistributed.